The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
The present disclosure generally relates to integrated circuits and more specifically relates to reducing transactional latency in address decoding.
Address decoding circuits are used in many integrated circuits, especially those relying on buses for example, microprocessors, FPGAs, and ASICS. Address decoding circuits typically contain digital logic that implements the address decode function.
An address decoding circuit in a computing system generates a chipselect signal for a target device upon receiving a request (an address decoding transaction) from a controller to access that target device. Examples of target devices or target circuits may include input/output devices, memory components, and connection components. A controller circuit controls the flow of data going to and from a computing system's main memory and other target devices.
An address decoding transaction comprises a controller sending requests (which may include memory-mapped or encoded addresses) to an address decoding circuit to read data from or write data to a target device. The encoded address is used by processing circuitry (for example, a central processing unit) to communicate with a controller. However, it is the address decoding circuit that then implements the address decoding function to generate a chipselect signal for the target device and forwards the results of the decoding to a selecting circuit, for example a de-multiplexer circuit. The selecting circuit then forwards the instructions from the controller to the appropriate target device.
In many systems, addresses are decoded in a single clock cycle. However, in more complicated computing systems, such as FPGAs that employ an interconnect architecture, use larger address widths, or interface with more addressable target circuits, address decoding is more complex and may become a critical path for the operation of the circuit. Therefore, there is a need for mitigating or eliminating the additional latency, while allowing a high operating frequency for address decoding transactions.